L3

ELEC 5804 Assignment #3: Gate Examination and Simulation

NOTE: When watching all the videos below, ensure that you play them full screen so that everything is readable (you can do this by clicking on the YouTube icon in the lower righthand corner to watch in YouTube, which allows you to view the videos at the full resolution of 1280x720). Also, if you try to watch them on a mobile device through 3G, YouTube downgrades the resolution and they look horrible. Probably you'll want to bring headphones to the lab in order to hear the audio.

NOTE: The name of the server has changed since I made these videos. So whenever I type or say "macopeland" replace that with "boothroyd". This is very important!

Part 1: Preparing for Assignment 3.

Follow the steps in the video below to prepare for Assignment 3:

Part 2: Creating a Library

We could use the library from assignment 2, but just to make sure that everyone is starting from the same point, let's create a new library for assignment 3 as follows:

2.1) Go to the Library Manager Window. 

2.2) Select: File → New → Library

2.3) For the "Name", enter "assignment03"

2.4) For "Technology File", select "Attach to an existing techfile".

2.5) Click OK, and in the form that appears, on "Attach to Technology Library", select "gpdk090", and click OK. The library "assignment03" is then created. You should see it added to the list of libraries available in the Library Manager window.

2.6) I made a library in my own account and changed the permissions for the library and my local directories so that you can read the library. You can add my library to your list of accessible libraries by going to the menu item Edit → Library Path and then adding the necessary library path information as well as a library name in the pop-up window that appears. This is demonstrated in the video below. 

2.7) After gaining access to my library, you should copy the single cellview within my library into your local assignment03 library. Again, this is demonstrated in the video below.

The video below demonstrates steps 2.1-2.7:

Part 3: Reverse Engineering

In this section we are going to create a schematic from a layout. This tedious procedure is used more than you will believe in "real life".  In fact, deriving a schematic from a given layout is a common question asked during job interviews.

Once you have the mystery cell in your library, look at the available cellviews for the component. You should see only a layout view. Your job is to create a transistor-level schematic for the layout, and demonstrate that the schematic is correct by performing LVS for the schematic and the extracted view of the supplied layout.

When creating your schematic, ensure that you use the correct components from the correct library.

When you examine the layout for the mystery cell try to locate the pain shapes that are present in the layout. You should be able to find two inputs and one output. As a further hint, the cell view is for a type of logical gate.

You can watch the following video to get some hints on how to approach this problem.

Part 4: Gate Simulation

In this section we will examine the switching points of a couple of gpdk090 gates.

4.1) In the library manager click on the assignment03 library, then click File→New→Cell View. In the form that pops up, enter gateSims as the Cell name, schematic as the View name, and click OK. Enter the schematic shown in the video below. Check and Save your schematic and resolve any errors/warnings. 

4.2) In the Virtuoso Schematic Editing window, go to Launch→ADE L. This will launch the Analog Design Environment application. 

4.3)  Watch the video below to learn how to set up the analog design environment to do a simulation of the operation of your gates. You will learn how to specify the model libraries, specify variables that are swept parameters, select outputs to be plotted, and set up an select the type a simulation that you wish to perform. 

4.6) More instructions are in Part 6 below.

 The video below demonstrates steps 4.1-4.6:

Part 5: Transient Simulation Involving Gates

5.1)  As described in the video below, in this section we will implement and simulate a ring oscillator constructed from simple inverters. In this case we build a three stage ring oscillator using the minimum drive strength inverters available in the design kit we use for this course.

5.2)  Pay special attention to the piecewise linear voltage source that is added to the feedback path in the ring oscillator schematic. It is therefore good reason, although it may not be obvious why. Try doing some research on oscillator simulation and "start-up kick".

The video below demonstrates the schematic setup and the simulation steps that you should perform for this section of the assignment:

5.3)  Cadence has a wide range of powerful tools that can simplify analysis and design of integrated circuits. Amongst those tools, one of my favorites is the calculator tool. In the video below I show you how to set up a simulation and use the calculator tool to demonstrate the oscillation frequency of an inverter-based ring oscillator as a function of the supply voltage. Watch the video, and use a similar technique to answer the last question of this assignment.

Part 6: Assignment Requirements

Your assignment hand-in must be typed. You can choose the format of your write up, but make sure that the following is included:

From Part 3:

• Q1. Include the schematic that you derived from the mystery cell layout. Identify the type of gate. Give a truth table for the gate. Hint: if you can’t identify the type of gate based on the schematic, then you could simulate the operation of your circuit as you did in assignment one for this course and thereby derive the truth table for the gate. [15 points]

From Part 4:

• Q2. In the class notes (on-line), it was determined that a standard CMOS NOR gate will be 4 times larger than a NAND gate for certain design criteria. Examine the layouts for the minimum size NOR gate and the minimum size NAND gate in the library. What is the size ratio? If the ratio is not approximately 4 to 1, explain why not (i.e. why would the ratio not be 4 to 1 and what does it affect?). [15 points]
• Q3. Referring to your simulation of the INV, NAND and NOR gates, comment on the switching points realized by these gates. How does the switching point of each gate affect the noise margin of each gate? [10 points]
• Q4. Using the extracted cellviews, obtain the sizes of the pfets and nfets in each gate (INV, NOR, NAND) and calculate the expected switching points. You may have to derive the switching points yourself (or find a good textbook with the derivation - your choice). Compared the calculated switching points to the simulated switching points. Give reasons for any differences. [15 points]
• Q5. What was the foremost design goal for this cell library, in your opinion? (e.g. was it gate switching point, or gate size - justify your answer). [10 points]

From Part 5:

• Q6. Explain the need for the piecewise linear voltage source in the feedback path of the ring oscillator. [5 points]
• Q7. Provide a plot of the transient output of the ring oscillator. [5 points]
• Q8. What is the simulated oscillation frequency? [5 points]
• Q9. Is the simulated oscillation frequency higher or lower than what we would measure in the lab if we actually fabricated this ring oscillator? Explain your answer. [5 points]
• Q10. Set up the simulation and use the parametric sweep in conjunction with the calculator tool to plot the total power consumption of the ring oscillator as a function of the supply voltage. Explain what procedure you used to generate the plot and include the plot in your assignment writeup. [20 points]