L1


97.5804 Lab #1: Introduction to Cadence

The purpose of this assignment is to familiarize each member of the ELEC5804 class with the some basic tools required for the course. It is important that you perform the assignment yourself. Make sure you understand each step. You should also gain some familiarity with UNIX commands.
Part 1: Starting Cadence
Watch the following YouTube video to learn how to get your Cadence directories set up, and also how to start Cadence.

NOTE #1: When watching all the videos below, ensure that you play them full screen so that everything is readable (you can do this by clicking on the YouTube icon in the lower righthand corner to watch in YouTube, which allows you to view the videos at the full resolution of 1280x720). Also, if you try to watch them on a mobile device through 3G, YouTube downgrades the resolution and they look horrible. Probably you'll want to bring headphones to the lab in order to hear the audio.

NOTE #2: The name of the server has changed since I made these videos. So whenever I type or say "macopeland" replace that with "boothroyd". This is very important!

NOTE #3: For some strange reason the tilde key ("~") is not working when I log in to the system. If that happens to you, let me know. For now, use "/home/maceacla/" instead of "~maceacla" in my first few steps of the video below. This seems to be related to the Mac computer I use.....if you use the PCs in the lab this should not be a problem.


 

  • The Cadence window that opens is called the Command Interpreter Window (CIW). Other "welcome" windows may also pop up the first time you use the Cadence tool. You can close these.
  • There is a HELP menu item in the upper-right corner of the CIW. Try it out, and see what manuals you can discover.
NOTE #4: You can access the Cadence tools manuals as PDF files starting in this directory:

 /CMC/tools/cadence/IC616_lnx86/doc

If you change to that directory and then run the command "find . -name "*.pdf" you will see the manuals. The manuals are placed in directories corresponding to the various Cadence tools.
  • The fastest way to learn Cadence is to have someone help you through the initial stages. The TA for the course can assist you if you get stuck.
Part 2: Bindkeys
Depending on which Cadence feature you are using, pressing a key invokes different actions. You can see the "bind keys" by going to Options menu in the CIW and selecting the "Bindkey..." menu item.
You should see some text scrolling in the CIW window when you hit a bind key. What Cadence is doing is calling a SKILL function that invokes the desired action. So, for example, there is a SKILL function named "ddsOpenLibManager()" that is called when you press the F6 key. Alternatively, you could type the command into the small text area in the CIW and invoke the function explicitly.
Watch the following video to learn about bind keys.
Part 3: Creating a Library and Creating a Design
You need to create a library, to which you will add your own designs. This is fairly straightforward and explained in the following video:

Part 4: Simulating the Gate Level Schematic with Verilog
In this part we use Verilog to simulate our cellview. Don't worry if you don't know Verilog enough to program. That comes later in the course. For now, Cadence will generate our Verilog code for us!

The following video will walk you through the steps required to simulate the schematic. You should enter the same schematic as shown in the video in your library.

You can use the following code for the stimulus file:

// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus.
initial
begin
a=1'b0;
b=1'b0;
c=1'b0;
#100; a=1'b0; b=1'b0; c=1'b0;
#100; a=1'b1; b=1'b0; c=1'b0;
#100; a=1'b0; b=1'b1; c=1'b0;
#100; a=1'b1; b=1'b1; c=1'b0;
#100; a=1'b0; b=1'b0; c=1'b1;
#100; a=1'b1; b=1'b0; c=1'b1;
#100; a=1'b0; b=1'b1; c=1'b1;
#100; a=1'b1; b=1'b1; c=1'b1;
end


 Part 5: Assignment Requirements
Please use this Google Form to submit your Laboratory answers to the questions posed below. 
Explain what a "Bind Key" does. For the first three letters of your first name, find the schematic entry functions associated with the keys corresponding to those letters. Give the names of the functions, and describe what happens when you press the bind keys. [10 points]
Name and briefly describe four types of cell views (eg. layout, extracted, schematic, etc.). [8 points]
Include a copy of the SimVision output in your report (a screen grab is fine). Create a truth table for the gate-level circuit from the Verilog simulation output. [5 points]
Write the boolean expression corresponding to the gate-level schematic. Show that the SimVision waveforms match the truth table. [12 points]

Simplify (or just rearrange into a different form) the boolean expression from (4), and add the necessary gates to your schematic to implement the new boolean expression. Include a picture of your updated schematic in your report. [15 points]
Re-simulate your cell, which should now contain two different implementations of the logic expression (one that I gave you in the video above, and one that you derived by simplifying the boolean expression). Show your results. [10 points]

Compare the outputs of the two logic implementations. Do they match? [10 points]

Comment on the relative complexity, and the required layout area, for the given logic circuit and the one you derived. [20 points]

Suppose that the circuit had 32 inputs instead of just 3. Explain how you would use the tools to obtain the truth table in this case (obviously you are not going to be able to go through the waveform by hand, so there must be another way to do it). [10 points]

HINTS:
In order to estimate the layout area, watch this video: